Verilator − Translate and simulate SystemVerilog code using C++/SystemC
verilator
−−help
verilator −−version
verilator −−binary −j 0 [options]
[source_files.v]... [opt_c_files.cpp/c/cc/a/o/so]
verilator −−cc [options] [source_files.v]...
[opt_c_files.cpp/c/cc/a/o/so]
verilator −−sc [options] [source_files.v]...
[opt_c_files.cpp/c/cc/a/o/so]
verilator −−lint−only −Wall
[source_files.v]...
The "Verilator" package converts all synthesizable, and many behavioral, Verilog and SystemVerilog designs into a C++ or SystemC model that after compiling can be executed. Verilator is not a traditional simulator, but a compiler.
For documentation see <https://verilator.org/verilator_doc.html>.
This is a short summary of the arguments to the "verilator" executable. See <https://verilator.org/guide/latest/exe_verilator.html> for the detailed descriptions of these arguments.
<file.v>
Verilog package, module, and top module filenames
<file.c/cc/cpp> Optional C++ files to compile in
<file.a/o/so> Optional C++ files to link in
+1364−1995ext+<ext> Use Verilog 1995 with file
extension <ext>
+1364−2001ext+<ext> Use Verilog 2001 with file
extension <ext>
+1364−2005ext+<ext> Use Verilog 2005 with file
extension <ext>
+1800−2005ext+<ext> Use SystemVerilog 2005 with
file extension <ext>
+1800−2009ext+<ext> Use SystemVerilog 2009 with
file extension <ext>
+1800−2012ext+<ext> Use SystemVerilog 2012 with
file extension <ext>
+1800−2017ext+<ext> Use SystemVerilog 2017 with
file extension <ext>
−−assert Enable all assertions
−−autoflush Flush streams after all $displays
−−bbox−sys Blackbox unknown $system calls
−−bbox−unsup Blackbox unsupported language
features
−−binary Build model binary
−−build Build model executable/library after
Verilation
−−build−dep−bin <filename>
Override build dependency Verilator binary
−−build−jobs <jobs> Parallelism for
−−build
−−cc Create C++ output
−−cdc Clock domain crossing analysis
−CFLAGS <flags> C++ compiler arguments for
makefile
−−clk <signal−name> Mark specified
signal as clock
−−no−clk <signal−name> Prevent
marking specified signal as clock
−−compiler <compiler−name> Tune for
specified C++ compiler
−−converge−limit <loops> Tune
convergence settle time
−−coverage Enable all coverage
−−coverage−line Enable line coverage
−−coverage−max−width <width>
Maximum array depth for coverage
−−coverage−toggle Enable toggle coverage
−−coverage−underscore Enable coverage of
_signals
−−coverage−user Enable SVL user coverage
−D<var>[=<value>] Set preprocessor define
−−debug Enable debugging
−−debug−check Enable debugging assertions
−−no−debug−leak Disable leaking
memory in −−debug mode
−−debugi <level> Enable debugging at a
specified level
−−debugi−<srcfile> <level>
Enable debugging a source file at a level
−−no−decoration Disable comments and
symbol decorations
−−default−language <lang> Default
language to parse
+define+<var>=<value> Set preprocessor define
−−dpi−hdr−only Only produce the DPI
header file
−−dump−defines Show preprocessor defines
with −E
−−dump−dfg Enable dumping DfgGraphs to
.dot files
−−dump−graph Enable dumping V3Graphs to
.dot files
−−dump−tree Enable dumping Ast .tree files
−−dump−tree−addrids Use short
identifiers instead of addresses
−−dump−<srcfile> Enable dumping
everything in source file
−−dumpi−dfg <level> Enable dumping
DfgGraphs to .dot files at level
−−dumpi−graph <level> Enable dumping
V3Graphs to .dot files at level
−−dumpi−tree <level> Enable dumping
Ast .tree files at level
−−dumpi−<srcfile> <level>
Enable dumping everything in source file at level
−E Preprocess, but do not compile
−−error−limit <value> Abort after
this number of errors
−−exe Link to create executable
−−expand−limit <value> Set expand
optimization limit
−F <file> Parse arguments from a file,
relatively
−f <file> Parse arguments from a file
−FI <file> Force include of a file
−−flatten Force inlining of all modules, tasks
and functions
−fno−<optimization> Disable internal
optimization stage
−G<name>=<value> Overwrite top−level
parameter
−−gate−stmts <value> Tune gate
optimizer depth
−−gdb Run Verilator under GDB interactively
−−gdbbt Run Verilator under GDB for backtrace
−−generate−key Create random key for
−−protect−key
−−getenv <var> Get environment variable
with defaults
−−get−supported <feature> Get if
feature is supported
−−help Display this help
−−hierarchical Enable hierarchical Verilation
−I<dir> Directory to search for includes
−−if−depth <value> Tune IFDEPTH
warning
+incdir+<dir> Directory to search for includes
−−inline−mult <value> Tune module
inlining
−−instr−count−dpi <value>
Assumed dynamic instruction count of DPI imports
−j <jobs> Parallelism for
−−build−jobs/−−verilate−jobs
−−l2−name <value> Verilog scope name
of the top module
−−language <lang> Default language
standard to parse
−LDFLAGS <flags> Linker pre−object
arguments for makefile
−−lib−create <name> Create a DPI
library
+libext+<ext>+[ext]... Extensions for finding modules
−−lint−only Lint, but do not make output
−−make <build−tool> Generate scripts
for specified build tool
−MAKEFLAGS <flags> Arguments to pass to make
during −−build
−−main Generate C++ main() file
−−main−top−name Specify top name
passed to Verilated model in generated C++ main
−−max−num−width <value>
Maximum number width (default: 64K)
−−Mdir <directory> Name of output object
directory
−−MMD Create .d dependency files
−−mod−prefix <topname> Name to
prepend to lower classes
−−MP Create phony dependency targets
+notimingchecks Ignored
−O0 Disable optimizations
−O3 High−performance optimizations
−O<optimization−letter> Selectable
optimizations
−o <executable> Name of final executable
−−no−order−clock−delay Disable
ordering clock enable assignments
−−output−split <statements> Split
.cpp files into pieces
−−output−split−cfuncs
<statements> Split model functions
−−output−split−ctrace
<statements> Split tracing functions
−P Disable line numbers and blanks with −E
−−pins−bv <bits> Specify types for
top−level ports
−−pins−sc−biguint Specify types for
top−level ports
−−pins−sc−uint Specify types for
top−level ports
−−pins−uint8 Specify types for
top−level ports
−−no−pins64 Don't use uint64_t's for
33−64 bit sigs
−−pipe−filter <command> Filter all
input through a script
−−pp−comments Show preprocessor comments
with −E
−−prefix <topname> Name of top−level
class
−−private Debugging; see docs
−−prof−c Compile C++ code with profiling
−−prof−cfuncs Name functions for profiling
−−prof−exec Enable generating execution
profile for gantt chart
−−prof−pgo Enable generating profiling
data for PGO
−−protect−ids Hash identifier names for
obscurity
−−protect−key <key> Key for symbol
protection
−−protect−lib <name> Create a DPI
protected library
−−public Debugging; see docs
−−public−params Mark all parameters as
public_flat
−−public−flat−rw Mark all variables,
etc as public_flat_rw
−pvalue+<name>=<value> Overwrite toplevel
parameter
−−quiet−exit Don't print the command on
failure
−−relative−includes Resolve includes
relative to current file
−−reloop−limit Minimum iterations for
forming loops
−−report−unoptflat Extra diagnostics for
UNOPTFLAT
−−rr Run Verilator and record with rr
−−savable Enable model save−restore
−−sc Create SystemC output
−−no−skip−identical Disable skipping
identical output
−−stats Create statistics file
−−stats−vars Provide statistics on
variables
−−no−std Prevent parsing standard library
−−structs−packed Convert all unpacked
structures to packed structures
−sv Enable SystemVerilog parsing
+systemverilogext+<ext> Synonym for
+1800−2017ext+<ext>
−−threads <threads> Enable multithreading
−−threads−dpi <mode> Enable
multithreaded DPI
−−threads−max−mtasks <mtasks>
Tune maximum mtask partitioning
−−timing Enable timing support
−−no−timing Disable timing support
−−timescale <timescale> Sets default
timescale
−−timescale−override <timescale>
Overrides all timescales
−−top <topname> Alias of
−−top−module
−−top−module <topname> Name of
top−level input module
−−trace Enable waveform creation
−−trace−coverage Enable tracing of
coverage
−−trace−depth <levels> Depth of
tracing
−−trace−fst Enable FST waveform creation
−−trace−max−array <depth>
Maximum bit width for tracing
−−trace−max−width <width>
Maximum array depth for tracing
−−trace−params Enable tracing of
parameters
−−trace−structs Enable tracing structure
names
−−trace−threads <threads> Enable FST
waveform creation on separate threads
−−no−trace−top Do not emit traces
for signals in the top module generated by verilator
−−trace−underscore Enable tracing of
_signals
−U<var> Undefine preprocessor define
−−no−unlimited−stack Don't disable
stack size limit
−−unroll−count <loops> Tune maximum
loop iterations
−−unroll−stmts <stmts> Tune maximum
loop body size
−−unused−regexp <regexp> Tune UNUSED
lint signals
−V Verbose version and config
−v <filename> Verilog library
−−verilate−jobs Job threads for Verilation
stage
−−no−verilate Skip Verilation and just
compile previously Verilated code
+verilog1995ext+<ext> Synonym for
+1364−1995ext+<ext>
+verilog2001ext+<ext> Synonym for
+1364−2001ext+<ext>
−−version Displays program version and exits
−−vpi Enable VPI compiles
−−waiver−output <filename> Create a
waiver file based on the linter warnings
−Wall Enable all style warnings
−Werror−<message> Convert warnings to
errors
−Wfuture−<message> Disable unknown message
warnings
−Wno−<message> Disable warning
−Wno−context Disable source context on warnings
−Wno−fatal Disable fatal exit on warnings
−Wno−lint Disable all lint warnings
−Wno−style Disable all style warnings
−Wpedantic Warn on compliance−test issues
−Wwarn−<message> Enable specified warning
message
−Wwarn−lint Enable lint warning message
−Wwarn−style Enable style warning message
−−x−assign <mode> Assign
non−initial Xs to this value
−−x−initial <mode> Assign initial Xs
to this value
−−x−initial−edge Enable initial
X−>0 and X−>1 edge triggers
−−xml−only Create XML parser output
−−xml−output XML output filename
−y <dir> Directory to search for modules
This is a short summary of the simulation runtime arguments, i.e. for the final Verilated simulation runtime models. See <https://verilator.org/guide/latest/exe_verilator.html> for the detailed description of these arguments.
+verilator+debug
Enable debugging
+verilator+debugi+<value> Enable debugging at a level
+verilator+error+limit+<value> Set error limit
+verilator+help Display help
+verilator+noassert Disable assert checking
+verilator+prof+exec+file+<filename> Set execution
profile filename
+verilator+prof+exec+start+<value> Set execution
profile starting point
+verilator+prof+exec+window+<value> Set execution
profile duration
+verilator+prof+vlt+file+<filename> Set PGO profile
filename
+verilator+rand+reset+<value> Set random reset
technique
+verilator+seed+<value> Set random seed
+verilator+V Verbose version and config
+verilator+version Show version and exit
The latest version is available from <https://verilator.org>.
Copyright 2003−2023 by Wilson Snyder. This program is free software; you can redistribute it and/or modify the Verilator internals under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
All Verilog and C++/SystemC code quoted within this documentation file are released as Creative Commons Public Domain (CC0). Many example files and test files are likewise released under CC0 into effectively the Public Domain as described in the files themselves.
verilator_coverage, verilator_gantt, verilator_profcfunc, make,
"verilator −−help" which is the source for this document,
and <https://verilator.org/verilator_doc.html> for detailed documentation.